The present invention relates to a method for etching TiO.sub.2, and particularly for selective patterning of thin TiO.sub.2 films.
TiO.sub.2 has highly desirable properties as an electronic material, particularly its dielectric constant. The dielectric constant of crystalline rutile is approximately 125, and as-deposited polycrystalline TiO.sub.2 can reliably be formed with a dielectric constant of 100 or better. Moreover, polycrystalline TiO.sub.2 has high resistivity, which (for polycrystalline material) can be 10.sup.8 ohm-cm or better.
Thus, it would be highly desirable to be able to use TiO.sub.2 for reasonably compact capacitors in integrated circuits. For example, a capacitor one mil square, having a TiO.sub.2 dielectric 100 nm thick atop a 10 nm SiO.sub.2 layer, would theoretically have a capacitance of 2.2 pF. Such capacitors are particularly desirable in communications and signal processing IC's. TiO.sub.2 could also be used to form large-value discrete capacitors.
In addition, TiO.sub.2 has the very desirable property that, when applied over a very thin silicon dioxide gate dielectric, the TiO.sub.2 tends to "plug" pinhole defects in the oxide, so that the yield rate on, e.g., 10 nm SiO.sub.2 gate dielectrics is greatly increased. Since the dielectric constant of TiO.sub.2 is so much larger than that of SiO.sub.2, TiO.sub.2 is electrically invisible, and the completed device behaves as if it had only a perfect 10 nm oxide in place. Thus, use of TiO.sub.2 as an extra layer in MIS gate dielectrics would permit very-high-yield fabrication of gate dielectrics which behaved as if they were extremely thin (10 nm or less).
However, realization of these theoretical advantages has hereto been in practice impossible, because TiO.sub.2 is chemically inert, and all efforts to wet etch it failed. For example, TiO.sub.2 is almost completely inert to HCl, H.sub.2 SO.sub.4, or HF. The rutile form of TiO.sub.2, which has particularly advantageous electrical properties, is also particularly inert.
A further area of application where the ability to etch TiO.sub.2 would be highly desirable is in multi-dielectric nonvolatile memory cells. In these cells, particularly where fast writing speeds are desired, very thin bottom dielectric layers are used, and a layer of TiO.sub.2 above the trapping layers provides good resistance to breakdown without degrading the electrical characteristics of the cell.
It is thus an object of the present invention to provide a method for etching TiO.sub.2.
It is a further object of the present invention to provide a method for etching TiO.sub.2 selectively with respect to photoresist.
It is a further object of the present invention to provide a method for etching TiO.sub.2 selectively with respect to aluminum.
It is a further object of the present invention to provide a method for etching a stack of TiO.sub.2 atop silicon dioxide (or nitride) such that a self-aligned etch of the TiO.sub.2 and of the silicon dioxide (or nitride) is performed.
It is a further object of the present invention to provide a method for etching a layer of TiO.sub.2 underneath a layer of polysilicon such that the etched patterns of TiO.sub.2 and polysilicon are self-aligned.